Learn to describe and validate digital logic in Verilog/SystemVerilog, from module creation to simulation and synthesis, using open-source tools such as Icarus Verilog and OpenLane. Master best practices for developing digital integrated circuits, test beds, and generating GDSII for real-world semiconductor projects.

Master functional verification methodologies to ensure the correct operation of your digital design prior to synthesis. Learn to create modular and reusable test environments with SystemVerilog and UVM (Universal Verification Methodology), developing testbeds that thoroughly validate your RTL design.

Explore the open RISC-V architecture from its basic instruction set to advanced extensions. Understand advanced concepts such as pipelines, multi-hierarchical memory system management, exception handling, and cache coherence. Implement your own RISC-V core in HDL, simulate and optimize it, and learn to integrate basic peripherals using open source toolchains such as GCC and Spike.

Learn how to transform your RTL layout design into a manufacturing-ready GDSII file. Master the synthesis workflow with OpenLane, timing optimization, DRC/LVS with KLayout, and automated mask generation. Upon completion, you'll have your own validated GDSII and understand the steps required to ship your chip to the foundry and produce it.